This application claims the priority of Korean Patent Application No. 2002-51630, filed Aug. 29, 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a delay locked loop which is partially turned on or off.
2. Description of the Related Art
Generally, a delay locked loop is utilized to receive an external clock signal generated by an external source and, in response, to output an internal clock signal having the same phase as the external clock signal. In a semiconductor memory device that operates in various operation modes, for example a DDR SDRAM (double data rate synchronous dynamic random access memory), a delay locked loop can be turned on or off in response to the lock time and operation speed of the delay locked loop, in order to reduce current consumption in the semiconductor memory device.
When a DDR SDRAM is first turned on, a phase of the delay locked loop is synchronized with an external clock signal after a predetermined time. Then, the delay locked loop can be turned off when the device is placed in a power-down mode, in order to reduce current consumption of the semiconductor memory device.
Subsequently, if the delay locked loop is turned on again, a phase of the output signal of the delay locked loop must, once again, be synchronized with the phase of the external clock signal. However, it takes time to synchronize the phase of the output signal of the delay locked loop with the phase of the external clock signal. Thus, it is difficult and inefficient to freely turn the delay locked loop on or off, in order to reduce the current consumption of the semiconductor memory device.
To solve the above-described problem, a method was proposed to store the synchronization information of an operating delay locked loop, prior to turning it off. Under this method, even if the delay locked loop is turned off and then on again, the internal signal of the delay locked loop having the same phase as an external clock signal can be readily output using the stored synchronization information. That is, the delay locked loop does not need to repeat the initial synchronization procedure performed when it was first turned on, and thus the time required for synchronizing the delay locked loop can be reduced.
However, even in the above case, the generation of the internal output signal of the delay locked loop can be limited by the self-delay of the delay locked loop according to the operation frequency of the delay locked loop; thus the operation of the delay locked loop must still be controlled according to the various operation modes of the semiconductor memory device.
In addition, in the case of turning the delay locked loop on or off in response to the operation mode of the semiconductor memory device, all portions of the delay locked loop are turned on or off. However, since some portions of the delay locked loop do not need to be turned on or off, turning all portions on or off unnecessarily increases the current consumption of the semiconductor memory device.